EEPROM array using 2 bit non-volatile memory cells and method of implementing same

ABSTRACT

An electrically erasable programmable read only memory block is provided which includes a plurality of rows of 2-bit non-volatile memory cells. Each of the memory cells has a first charge trapping region for storing a first bit and a second charge trapping region for storing a second bit. Each pair of adjacent memory cells in each row are coupled to share a common diffusion bit line. A plurality of metal bit lines are coupled to the diffusion bit lines through high voltage select transistors. In one embodiment, there are half as many metal bit lines as diffusion bit lines.

FIELD OF THE INVENTION

[0001] The present invention relates to non-volatile memory cells. Morespecifically, the present invention relates to a method and structure ofusing a 2-bit flash memory cell to form an electrically erasableprogrammable read only memory (EEPROM) array.

RELATED ART

[0002]FIG. 1 is a cross sectional view of a conventional 1-bitnon-volatile semiconductor memory cell 10 that utilizes asymmetricalcharge trapping. 1-bit memory cell 10, which is fabricated in p-typesubstrate 12, includes n+ source region 14, n+ drain region 16, channelregion 17, silicon oxide layer 18, silicon nitride layer 20, siliconoxide layer 22, and control gate 24. Oxide layer 18, nitride layer 20and oxide layer 22 are collectively referred to as ONO layer 21. Memorycell 10 operates as follows. A programming operation is performed byconnecting source region 14 to ground, connecting drain region 16 to aprogramming voltage of about 9 Volts, and connecting control gate 24 toa voltage of about 10 Volts. As a result, electrons are accelerated fromsource region 14 to drain region 16. Near drain region 16, someelectrons gain sufficient energy to pass through oxide layer 18 and betrapped in nitride layer 20 in accordance with a phenomenon known as hotelectron injection. Because nitride layer 20 is non-conductive, theinjected charge remains localized within charge trapping region 26 innitride layer 20.

[0003] Memory cell 10 is read by applying 0 Volts to the drain region16, 2 Volts to the source region 14, and 3 volts to the gate electrode.If charge is stored in charge trapping region 26 (i.e., memory cell 10is programmed), then memory cell does not conduct current under theseconditions. If there is no charge stored in charge trapping region 26(i.e., memory cell 10 is erased), then memory cell 10 conducts currentunder these conditions. The current, or lack of current, is sensed by asense amplifier to determine the state of memory cell 10.

[0004] Note that the polarity of the voltage applied across sourceregion 14 and drain region 16 is reversed during the program and readoperations. That is, memory cell 10 is programmed in one direction (withsource region 14 grounded), and read the opposite direction (with drainregion 16 grounded). As a result, the read operation is referred to as areverse read operation. Memory cell 10 is described in more detail inU.S. Pat. No. 5,768,192.

[0005] Memory cell 10 can also be controlled to operate as a 2-bitnon-volatile semiconductor memory cell. To accomplish this, memory cell10 is controlled to use a second charge trapping region in nitride layer20, which is located adjacent to source region 14. FIG. 2 illustratesboth the first charge trapping region 26 (described above in connectionwith FIG. 1), and the second charge trapping region 28 in dashed lines.The second charge trapping region 28 is used to store a chargerepresentative of a second bit. The second charge trapping region 28 isprogrammed and read in a manner similar to the first charge trappingregion 26. More specifically, the second charge trapping region 28 isprogrammed and read by exchanging the source and drain voltagesdescribed above for programming and reading the first charge trappingregion 26. Thus, the second charge trapping region 28 is programmed byapplying 0 Volts to drain region 16, applying 9 Volts to source region14 and applying 10 Volts to control gate 24. Similarly, the secondcharge trapping region 28 is read by applying 0 Volts to source region14, 2 Volts to drain region 16, and 3 Volts to control gate 24.

[0006] Note that because nitride layer 20 is non-conductive, the chargesstored in the first and second charge trapping regions 26 and 28 remainlocalized within nitride layer 20. Also note that the state of the firstcharge trapping region 26 does not interfere with the reading of thecharge stored in the second charge trapping region 28 (and vice versa).Thus, if the first charge trapping region 26 is programmed (i.e., storescharge) and the second charge trapping region 28 is not programmed(i.e., does not store charge), then a reverse read of the first chargetrapping region will not result in significant current flow. However, areverse read of the second bit will result in significant current flowbecause the high voltage applied to drain region 16 will result inunperturbed electronic transfer in the pinch off region adjacent tofirst charge trapping region 26. Thus, the information stored in thefirst and second charge trapping regions 26 and 28 is read properly.

[0007] Similarly, if both the first and second charge trapping regionsare programmed, a read operation in either direction will result in nosignificant current flow. Finally, if neither the first charge trappingregion 26 nor the second charge trapping region 28 is programmed, thenread operations in both directions will result in significant currentflow.

[0008] Because the 1-bit and 2-bit implementations of memory cell 10 arerelatively new, the manner of using this memory cell 10 in a memory cellarray has not yet been fully developed. It would therefore be desirableto have a memory array structure that allows memory cell 10 to beimplemented as an electrically erasable programmable read only memory(EEPROM). For purposes of this disclosure, an EEPROM array is defined asa non-volatile memory array that can be erased on a word-by-word basis.This is in contrast to a flash memory array, which is defined as anon-volatile memory array that cannot be erased on a word-by-word basis,but which must be erased in blocks. It would further be desirable if theEEPROM array architectures could be fabricated using a standard flashprocess.

SUMMARY

[0009] Accordingly, the present invention provides structures andmethods for implementing an EEPROM array using 2-bit non-volatile memorycells. As described above, each memory cell has a first charge trappingregion for storing a first bit and a second charge trapping region forstoring a second bit.

[0010] In one embodiment, the EEPROM array includes an array of 2-bitmemory cells arranged in a plurality of rows and columns. Each row ofmemory cells shares a word line, which provides a common connection tothe control gates of the memory cells in the row. Also within each row,the first charge trapping region of each memory cell is coupled to thesecond charge trapping region of an adjacent memory cell by a diffusionbit line. Note that for purposes of the present disclosure, a chargetrapping region is defined as being “coupled” to its nearest diffusionbit line, even though there is no physical connection between thediffusion bit line and the charge trapping region. In this embodiment,each diffusion bit line provides connections to memory cells in aplurality of rows.

[0011] In one embodiment, an erase operation is performed by applying avoltage of about 0 Volts to the word line of the selected memory cell,and a voltage of about 8 Volts to the diffusion bit line of the selectedmemory cell. Other voltages can be used in other embodiments. Becauseadjacent memory cells share the same word line and the same diffusionbit line, erasing the first charge trapping region of a memory cell willincidentally erase the second charge trapping region of the adjacentmemory cell. Moreover, memory cells in other rows that are coupled tothe same diffusion bit line will also receive the erase voltage of 8Volts, potentially subjecting these memory cells to erase conditions.

[0012] The present invention compensates for the above-described eraseconditions as follows. A storage device is coupled to the diffusion bitlines of the array. A memory control circuit is coupled to control theEEPROM array and the storage device. Prior to erasing the first chargetrapping region of a first memory cell, the memory control circuit readsa plurality of bits from the array, and causes these bits to be writtento the storage device. The bits read from the array are selected toinclude all bits that will be incidentally erased when the first chargetrapping region is erased (e.g., the bit stored in the second chargetrapping region of the memory cell adjacent to the first memory cell andthe other bits sharing the same diffusion bit line). After these bitsare stored in the storage device, the memory control circuit causes thefirst charge trapping region to be erased. After the erase operation iscompleted, the memory control circuit causes all of the bits in thestorage device to be restored to the array. The net effect of theseoperations is to erase only the first charge trapping region of thefirst transistor. Because the array can be erased on a word-by-wordbasis in this manner, the array advantageously operates as an EEPROMarray.

[0013] In another embodiment of the present invention, each row ofmemory cells is accessed through a dedicated set of select transistors,and the memory cells in each row have dedicated diffusion bit lines.That is, the diffusion bit lines do not extend to a plurality of rows.As a result, erasing the first charge trapping region of a firsttransistor only results in the incidental erasing of the second chargetrapping region of an adjacent second transistor. Thus, in one variationof this embodiment, the bit stored in the second charge trapping regionis written to the storage device, the first charge trapping region iserased, and the bit from the second charge trapping region is restoredfrom the memory storage device to the second charge trapping region ofthe adjacent second transistor. Again, because this array can be erasedon a word-by-word basis, this array advantageously operates as an EEPROMarray.

[0014] In another variation of this embodiment, the second chargetrapping region of the adjacent second transistor is simply not used tostore data. As a result, an erase operation only erases one meaningfulbit (i.e., the bit stored in the first charge trapping region of thefirst transistor). Because this array can be erased on a word-by-wordbasis, this array advantageously operates as an EEPROM array.

[0015] The present invention will be more fully understood in view ofthe following description and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0016]FIG. 1 is a cross sectional diagram illustrating a conventional1-bit non-volatile memory cell;

[0017]FIG. 2 is a cross sectional diagram illustrating a conventional2-bit non-volatile memory cell;

[0018]FIG. 3 is a schematic diagram illustrating a memory block thatuses the 2-bit memory cells of FIG. 2;

[0019]FIG. 4A is an isometric view of memory cells of the memory blockof FIG. 3;

[0020]FIG. 4B illustrates the same isometric view as FIG. 4A, with thelocations of the memory cells highlighted in dashed lines;

[0021]FIG. 5 is a cross sectional view of selected memory cells of FIG.4A, taken along a word line;

[0022]FIG. 6 is a schematic diagram illustrating additional diffusionbit lines, metal bit lines and select transistors connected at the leftand right ends of a memory array in accordance with one embodiment ofthe present invention;

[0023]FIG. 7 is a block diagram of a circuit that emulates per biterasing of the memory block of FIG. 3 in accordance with one embodimentof the present invention; and

[0024]FIG. 8 is a schematic diagram of a memory block in accordance withanother embodiment of the present invention.

DETAILED DESCRIPTION

[0025]FIG. 3 is a schematic diagram illustrating a memory block 100 inaccordance with one embodiment of the present invention. Memory block100 uses a plurality of 2-bit memory cells identical to 2-bit memorycell 10 (FIG. 2). Memory block 100 includes seven full columns of memorycells, two columns of memory cells that are shared with adjacent memoryblocks, and thirty-two rows of memory cells. The rows extend along afirst axis, and the columns extend along a second axis, perpendicular tothe first axis. The memory cells in the seven full columns areidentified as memory cells M_(X,Y), where X and Y represent the row andcolumn locations, respectively, of the memory cells within memory block100. The shared memory cells on the left border of memory block 100 areidentified as memory cells ML_(X), and the shared memory cells on theright border of memory block 100 are identified as memory cells MR_(X).Thus, memory block includes memory cells M_(0,0)-M_(31,6) and sharedmemory cells ML₀-ML₃₁ and MR₀-MR₃₁.

[0026] Each of the memory cells includes two charge trapping regions,namely, a left charge trapping region and a right charge trappingregion. The charge trapping regions of memory cell M_(0,1) are labeledas left charge trapping region 1 and right charge trapping region 2.Similarly, the charge trapping regions of memory cell M_(0,2) arelabeled as left charge trapping region 3 and right charge trappingregion 4.

[0027] The source and drain regions of memory cells M_(0,0)-M_(31,6) areformed by diffused regions 101-108, which extend in parallel along thesecond axis. As described in more detail below, diffused regions 101-108also operate as bit lines within memory block 100. Consequently,diffused regions 101-108 are hereinafter referred to as diffusion bitlines.

[0028] ONO structures 111-117 are located between adjacent diffusion bitlines 101-108. For example, ONO structure 111 is located betweendiffusion bit lines 101 and 102. The gates of the memory cells in eachrow are commonly connected to a word line. More specifically, the memorycells of rows 0-31 are connected to word lines WL₀-WL₃₁, respectively.

[0029]FIG. 4A is an isometric view of memory cells M_(0,0), M_(0,1),M_(1,0), and M_(1,1). FIG. 4B illustrates the same isometric view asFIG. 4A, with the locations of memory cells M_(0,0), M_(0,1), M_(1,0),and M_(1,1) highlighted in dashed lines. FIG. 5 is a cross sectionalview of memory cells M_(0,0) and M_(0,1) along the first axis throughword line WL₀. Diffusion bit lines 101-103 are n-type regions formed ina p-type silicon semiconductor substrate 110. Diffusion bit lines101-103 can also be formed in a p-well region. Bit line insulatingregions 124 are formed over the diffusion bit lines 101-103. Bit lineinsulating regions 124 can be, for example, silicon oxide having athickness of approximately 600 Å. Note that bit line insulating regions124 are an order of magnitude thinner than conventional field oxide.Because the memory cells in memory block 100 do not require field oxidefor isolation, memory block 100 can be referred to as a fieldless array.ONO structures 111 and 112 extend over bit line insulating regions 124,diffusion bit lines 101-103 and substrate 110 in the manner illustrated.Word lines WL₀ and WL₁, which are polycide or salicide structures thatinclude a layer of conductively doped polycrystalline silicon 126 and anoverlying layer of metal silicide 127, extend over ONO structures 111and 112 (and bit line insulating regions 124). Word lines WL₀ and WL₁form the control gates of memory cells M_(0,0), M_(0,1) M_(1,0), andM_(1,1). The above-described structures of memory block 100 arefabricated using flash processing steps. The fabrication of memory block100 is described in more detail in commonly owned, pending U.S. patentapplication Ser. No. 09/244,316, entitled “METHODS FOR FABRICATING ASEMICONDUCTOR CHIP HAVING CMOS DEVICES AND A FIELDLESS ARRAY” by EfraimAloni, which is hereby incorporated by reference.

[0030] Returning now to FIG. 3, the 2-bit memory cells of memory block100 are accessed through high-voltage select transistors 131-138 andmetal bit lines 141-144. Metal bit lines 141-144 are located in aninterconnect layer that extends over the above-described elements ofmemory block 100. High-voltage select transistors 131-138 are designedto have gate oxide sufficient to withstand the high voltages requiredfor programming and erasing the memory cells. In general, selecttransistors 131-138 are controlled to selectively connect metal bitlines 141-144 to diffusion bit lines 101-108. The first power terminalsof select transistors 131-138 are coupled to diffusion bit lines101-108, respectively. The second power terminals of select transistors131 and 133 are coupled to metal bit line 141. The second powerterminals of select transistors 132 and 134 are coupled to metal bitline 142. The second power terminals of select transistors 135 and 137are coupled to metal bit line 143. The second power terminals of selecttransistors 136 and 138 are coupled to metal bit line 144. The gates ofselect transistors 131 and 135 are commonly connected to a first selectline S₁, while the gates of select transistors 133 and 137 are commonlyconnected to a second select line S₂. Similarly, the gates of selecttransistors 132 and 136 are commonly connected to a third select lineS₃, while the gates of select transistors 134 and 138 are commonlyconnected to a fourth select line S₄.

[0031] The memory cells in memory block 100 are accessed as follows. Twoof the select lines S₁-S₄ are pulled high, thereby turning on the selecttransistors coupled to these two select lines, and two of the selectlines S₁-S₄ are pulled low, thereby turning off the select transistorscoupled to these two select lines. The turned on select transistorscouple two columns of memory cells to the metal bit lines 141-144.

[0032] For example, when select lines S₂ and S₃ are pulled high, andselect lines S₁ and S₄ are pulled low, metal bit lines 141-142 arecoupled to access the second column of memory cells, and metal bit lines143-144 are coupled to access the seventh column of memory cells. Morespecifically, the logic high select lines S₂ and S₃ cause selecttransistors 132, 133, 136 and 137 to turn on, and the logic low selectlines S₁ and S₄ cause select transistors 131, 134, 135 and 138 to turnoff. Consequently, diffusion bit line 102 is coupled to metal bit line142 and diffusion bit line 103 is coupled to metal bit line 141.Similarly, diffusion bit line 106 is coupled to metal bit line 144 anddiffusion bit line 107 is coupled to metal bit line 143. As a result,signals provided on metal bit lines 141 and 142 are provided to controlthe memory cells in the second column of memory block 100, and signalsprovided on metal bit lines 143 and 144 are provided to control thememory cells in the seventh column of memory block 100.

[0033] A plurality of memory blocks, identical to memory block 100 canbe coupled together along the first and second axes, thereby forming alarger memory array. Shared memory cells are formed at the interfacesbetween memory blocks along the first axis. More specifically, theright-most shared memory cells MR₀-MR₃₁ of one memory block combine withthe left-most shared memory cells ML₀-ML₃₁ of an adjacent memory blockto form another column of memory cells. Stated another way, theright-most diffusion bit line of one memory block combines with theleft-most diffusion bit line of an adjacent memory block (along with theONO layer located there between) to form a shared column of memorycells. This shared column of memory cells is accessed by the right-mostmetal line in a memory block and the left-most metal bit line in theright-adjacent memory block. This shared column of memory cells isaccessed when select lines S₁ and S₄ are pulled high and select lines S₂and S₃ are pulled low. Note that under these conditions, access isprovided to the following memory cells in memory block 100: sharedmemory cells ML₀-ML₃₁, shared memory cells MR₀-MR₃₁ and the fourthcolumn of memory cells M_(0,3)-M_(31,3). Because each column of sharedmemory cells counts as a half column within memory block 100, there areeffectively two accessed columns within memory block 100 under theseconditions.

[0034] In accordance with one embodiment of the present invention, amemory array is formed by coupling 64 memory blocks identical to memoryblock 100 along the first axis. This memory array can have any number ofmemory blocks connected along the second axis. Because each memory blockhas four metal bit lines, the resulting memory array has a 256 metal bitlines associated with these 64 memory blocks. In this memory array, anadditional diffusion bit line, metal bit line and select transistor mustbe added to the left side of each of the left-most memory blocks of thearray. This enables the shared memory cells ML₀-ML₃₁ of the left-mostmemory blocks to be accessed. Similarly, an additional diffusion bitline, metal bit line, and select transistor must be added to the rightside of each of the right-most memory blocks of the array, therebyenabling the shared memory cells MR₀-MR₃₁ of the right-most memoryblocks to be accessed.

[0035]FIG. 6 is a schematic diagram illustrating the additionaldiffusion bit lines, metal bit lines and select transistors that areconnected at the left and right edges of the memory array. In FIG. 6,only the left-most portion of a left-most memory block 664 and theright-most portion of a right-most memory block 601 are illustrated(i.e., memory blocks 602-663, which are located between memory blocks601 and 664, are not illustrated). Because the left-most memory block664 and the right-most memory block 601 are identical to memory block100, the illustrated elements of memory blocks 664 and 601 are labeledwith the same reference numbers as memory block 100. However, the metalbit lines are labeled as MBL[N] in FIG. 6, where N is an integer thatidentifies the metal bit line in the array. Thus, the right-most metalbit lines in memory block 601 are labeled MBL[2] and MBL[1]. Similarly,the left-most metal bit lines in memory block 664 are labeled asMBL[256] and MBL[255]. The 256 metal bit lines in the 64 memory blockscoupled along the first axis are therefore identified as metal bit linesMBL[256:1].

[0036] Diffusion bit line 110, metal bit line MBL[257] and selecttransistor 130 are located at the left edge of the array. Memory cellsML₀-ML₃₁ are formed between diffusion bit line 110 and diffusion bitline 101 of memory block 664. Select transistor 130 is connected betweendiffusion bit line 110 and metal bit line MBL[257]. The gate of selecttransistor 130 is coupled to select line S₄.

[0037] Similarly, diffusion bit line 109, metal bit line MBL[0] andselect transistor 139 are located at the right edge of the array. Memorycells MR₀-MR₃₁ are formed between diffusion bit line 109 and diffusionbit line 108 of memory block 601. Select transistor 139 is connectedbetween diffusion bit line 109 and metal bit line MBL[0]. The gate ofselect transistor 139 is coupled to select line S₁.

[0038] Because of the two additional metal bit lines MBL[257] and MBL[0]provided at the left and right edges of the memory array, the memoryarray has a total of 258 metal bit lines (i.e., MBL[257:0]).

[0039] Access having been provided to all of the memory cells, program,read and erase operations are performed as follows.

[0040] Read Operation

[0041] A single bit of memory block 100 is read as follows. The wordline associated with the selected memory cell is maintained at a readvoltage of 3 volts, while the word lines associated with thenon-selected memory cells are held at a voltage of 0 Volts. One of thediffusion bit lines of the selected memory cell is held at a voltage of2 Volts, and the other diffusion bit line of the selected memory cell iscoupled to a sense amplifier (and held at a voltage of about 0 Volts),such that a reverse read conditions exist for the selected memory cell.For example, to read the right charge trapping region 2 of memory cellM_(0,1), the word line WL₀ is held at a voltage of 3 Volts, while theword lines WL₁-WL₃₁ are held at 0 Volts. A voltage of 2 Volts is appliedto diffusion bit line 102, and diffusion bit line 103 is coupled to asense amplifier (0 Volts), thereby creating reverse read conditions forright charge trapping region 2 of memory cell M_(0,1). Under theseconditions, the non-selected memory cells are neither read nordisturbed.

[0042] Program Operation

[0043] For a programming operation, the word line associated with theselected memory cell is held at a programming voltage of 11 volts, whilethe word lines associated with the non-selected memory cells are held ata voltage of 0 Volts. The source region of the selected memory cell ismaintained at a voltage of 0 Volts, and the drain region of the selectedmemory cell is maintained at a voltage of 5.5 Volts. For example, toprogram the right charge trapping region 2 of memory cell M_(0,1), theword line WL₀ is held at a voltage of 11 Volts, while the word linesWL₁-WL₃₁ are held at 0 Volts. A voltage of 5.5 Volts is applied todiffusion bit line 103, and a voltage of 0 Volts is applied to diffusionbit line 102, thereby creating a program condition for right chargetrapping region 2 of memory cell M_(0,1). The duration of theprogramming operation is on the order of micro-seconds. Note that theduration of the programming operation is not long enough and the applieddrain voltage of 5.5 Volts is not high enough to cause the non-selectedmemory cells to be erased during the programming operation.

[0044] Erase Operation

[0045] An erase operation is performed by applying 0 Volts to the gateof a selected memory cell and 8 Volts to the drain region of theselected memory cell. In general, erase operations in memory block 100cannot be limited to a single memory cell. For example, an attempt toerase the right charge trapping region 2 of memory cell M_(0,1) wouldproceed as follows. First, the select transistors 132 and 133 are turnedon, thereby providing access to the second column of memory block 100 bycoupling metal bit lines 141 and 142 to diffusion bit lines 103 and 102,respectively. An erase voltage of 8 Volts is applied to diffusion bitline 103, and an erase voltage of 0 Volts is applied to word line WL₀.

[0046] Under these conditions, the right charge trapping region 2 ofmemory cell M_(0,1) is erased. However, under these conditions, the leftcharge trapping region 3 of the adjacent memory cell M_(0,2) is alsoerased. Moreover, if the non-selected word lines WL₁-WL₃₁ are maintainedat 0 Volts, then the right charge trapping regions of all of the memorycells in the second column and the left charge trapping regions of allof the memory cells in the third column are also erased. As a result,the erase operation will erase a minimum of 64 bits. Raising thevoltages on the non-selected word lines may eliminate the eraseconditions, but may, in turn, create undesirable programming conditions.

[0047] Because a normal erase operation will erase at least 64 bits, oneerase option is to erase the entire memory block 100 at the same time,thereby operating memory block 100 as a flash memory. To erase theentire memory block 100, all of the word lines WL₀-WL₃₁ are held at 0Volts, and all of the diffusion bit lines 101-108 are held at a voltageof 8 Volts. The duration of the erase operation is on the order ofmilli-seconds.

[0048] As described above, a normal erase operation in memory block 100will erase at least 64 bits. However, to operate memory block 100 as anEEPROM, there must be a mechanism for erasing data on a word-by-wordbasis. It would therefore be desirable to modify the erase operation ofmemory block 100, such that memory block 100 can be erased on aword-by-word basis. In one embodiment of the present invention, themethod of operating memory block 100 is modified such that memory block100 emulates EEPROM. To accomplish this emulation, a single bit ofmemory block 100 is erased in the following manner.

[0049]FIG. 7 is a block diagram of an erase emulation structure 200 thatemulates word-by-word erasing in a memory array that uses memory block100. Emulation structure 200 includes memory array 201, bit line controlcircuit 202, sense amplifier circuit 203, 64 word storage device 204 andmemory control circuit 205. Memory array 201 is formed from a pluralityof memory blocks identical to memory block 100. The metal bit lines ofmemory array 201 are routed to bit line control circuit 202. Bit linecontrol circuit 202 is controlled to apply the appropriate read, programand erase voltages to the metal bit lines MBL[257:0]. During a readoperation, bit line control circuit 202 also routes an addressed set ofeight bit lines to sense amplifier circuit 203 in response to a columnaddress received from memory control circuit 205. Bit line controlcircuit 202 is described in more detail in commonly owned, U.S. Pat. No.6,081,456 which issued Jun. 27, 2000, by Oleg Dadashev, entitled BITLINE CONTROL CIRCUIT FOR A MEMORY ARRAY USING 2-BIT NON-VOLATILE MEMORYCELLS, which is hereby incorporated by reference.

[0050] The number of bit lines routed to sense amplifier circuit 203 isselected to correspond with the word width of memory array 201. In thedescribed example, this word width is 8 bits. Note that each bit of the8-bit word routed to sense amplifier circuit 203 is received from adifferent memory block within memory array 201. Sense amplifier circuit203 is coupled to storage device 204. Storage device 204 is configuredto store 64 8-bit values. Memory control circuit 205 provides addresssignals to control the access of storage device 204. Storage device 204can be, for example, a static random access memory (SRAM).

[0051] The operation of erase emulation circuit 200 will now bedescribed in connection with an example. This example describes theprocess required to erase one bit in a memory block within memory array201. However, it is understood that this process is simultaneouslyperformed for 8 bits in 8 different memory blocks, such that an entireword is erased. The present example assumes that it is desired to erasethe bit stored in the right charge trapping region 2 of memory cellM_(0,1) (FIG. 3).

[0052] First, memory control circuit 205 controls memory array 201 andbit line control circuit 202 such that the bit stored in the rightcharge trapping region of memory cell M_(0,1) is read. Memory controlcircuit 205 further controls bit line control circuit 202 to route thisbit (along with the seven other addressed bits of the word) to senseamplifier circuit 203 and storage device 204. Memory control circuit 205causes the accessed bit (word) to be written to the first entry ofstorage device 204.

[0053] Memory control circuit 205 then sequentially performs readaccesses of the right charge trapping regions of memory cellsM_(1,1)-M_(31,1). That is, memory control circuit 205 sequentially readsthe bits from the right charge trapping regions of all of the memorycells in the second column. The bits read are stored in sequentiallocations in storage device 204 under the control of memory controlcircuit 205.

[0054] Memory control circuit 205 then sequentially performs readaccesses of the bits stored in the left charge trapping regions ofmemory cells M_(0,2)-M_(31,2). That is, memory control circuit 205causes the bits from the left charge trapping regions of all of thememory cells in the third column to be sequentially read. These bits arestored in sequential locations in storage device 204 under the controlof memory control circuit 205.

[0055] After these 64 read operations have been completed, all of thebits that would have been erased by erasing the right charge trappingregion 2 of memory cell M_(0,1) are stored in storage device 204. Atthis time, memory control circuit 205 performs an erase operation thaterases the right charge trapping region 2 of memory cell M_(0,1). Asdescribed above, this erase operation also erases the right chargetrapping regions of memory cells M_(1,1)-M_(31,1) and the left chargetrapping regions of memory cells M_(0,2)-M_(31,2).

[0056] After the erase operation has been completed, memory controlcircuit 205 performs 63 consecutive programming operations to restorethe bits from storage device 204 to the right charge trapping regions ofmemory cells M_(1,)-M_(31,1) and the left charge trapping regions ofmemory cells M_(0,2)-M_(31,2). That is, the bits are restored to theleft charge trapping regions of all of the memory cells in the thirdcolumn, and to the right charge trapping regions of all of the memorycells in the second column, except for the right charge trapping regionof memory cell M_(0,1). The net effect of these operations is to eraseonly the bit stored in the right charge trapping region of memory cellM_(0,1). In the foregoing manner, memory array 201 can be erased on aword-by-word basis, thereby enabling memory array 201 to be operated asan EEPROM array. Note that a bit stored in the left charge trappingregion of a memory cell can be erased in a similar manner.

[0057] The time required to read the 64 bits from memory array 201 is onthe order of nano-seconds. The time required to perform the eraseoperation is on the order of tens of milliseconds. The time required tore-program each of the 63 bits back into memory array 201 is on theorder of micro-seconds. Consequently, the time required to read andrestore the 63 bits that are not being erased is a small percentage(i.e., about 1 percent) of the total erase time.

[0058] In a variation of the above-described embodiment, memorycontroller 205 does not cause the bit to be erased to be read and storedin storage device 204. In the above described example, the bit stored inthe right charge trapping region of the memory cell M_(0,1) would not beread (since this bit is going to be subsequently erased). As a result,only 63 read operations are performed prior to the erase operation.

[0059] It is understood that the endurance of memory array 201 may belimited in the present embodiment, because on average, the memory cellsof memory array 201 will be erased and programmed approximately 63 timesmore often than memory cells in an equivalent flash memory. However, itis understood that this loss of endurance is acceptable in certainapplications where memory array 201 is not expected to be re-programmeda large number of times.

[0060]FIG. 8 is a schematic diagram of a memory block 300 in accordancewith another embodiment of the present invention. Because memory block300 is similar to memory block 100 (FIG. 3), similar elements in FIGS. 3and 8 are given similar reference numbers. Thus, memory block 300includes memory cells M_(0,0)-M_(0,6), shared memory cells ML₀ and MR₀,select transistors 131-138 and metal bit lines 141-144. Diffusion bitlines 101-108 of memory block 100 are replaced by diffusion bit lines201-208 in memory block 300. As illustrated in FIG. 8, memory block 300has only one row of memory cells, which includes memory cellsM_(0,0)-M_(0,6) and shared memory cells ML₀ and MR₀. As a result, thediffusion bit lines 201-208 of memory block 200 are much shorter alongthe second axis than the diffusion bit lines 101-108 of memory block100. Select transistors 131-138 are connected to diffusion bit lines201-208 in the same manner that select transistors 131-138 are connectedto diffusion bit lines 101-108 in memory block 100 (FIG. 3). Similarly,select transistors 131-138 are connected to metal bit lines 141-144 andselect lines S1-S4 in the manner previously described for memory block100 (FIG. 3). A plurality of memory blocks identical to memory block 300can be coupled together along the first and second axes, thereby forminga larger memory array.

[0061] Memory block 300 is controlled as follows. The memory cells ofmemory block 300 are programmed in the same manner as the memory cellsof memory block 100. However, only the memory cells being programmed areexposed to the bit line programming voltages. As a result, there is lesschance for disturb conditions to exist in non-selected memory cellsduring a programming operation in memory block 300. The memory cells ofmemory block 300 are read in the same manner as the memory cells ofmemory block 100.

[0062] In one embodiment, erase operations are carried out in memoryblock 300 in accordance with the following example. To erase the bitstored in the right charge trapping region 2 of memory cell M_(0,1), thefollowing steps are performed. First, the bit stored in the left chargetrapping region 3 of the right-adjacent memory cell M_(0,2) is read frommemory block 300 and stored in a storage device. This storage device issimilar to storage device 204 (FIG. 7), but has a depth of one wordinstead of 64 words. An erase operation is then performed to erase thebit stored in the right charge trapping region 2 of memory cell M_(0,1).As described above, this erase operation also erases the bit stored inthe left charge trapping region 3 of right-adjacent memory cell M_(0,2).After the erase operation has been completed, the bit previously readfrom the left charge trapping region 3 of memory cell M_(0,2) is writtenfrom the storage device back to the left charge trapping region 3 ofmemory cell M_(0,2). The net result is that the right charge trappingregion 2 of memory cell M_(0,1) is erased. Although the present exampleis described in connection with a single bit in memory block 300, it isunderstood that another seven bits in similar memory blocks arecontrolled in the same manner in parallel, such that an 8-bit word iserased during an erase operation. Moreover, it is also understood thatthe left charge trapping region 3 of memory cell M_(0,2) can be erasedby reading the bit stored in the right charge trapping region 2 ofmemory cell M_(0,1), performing the erase operation, and then restoringthe bit to the right charge trapping region 2 of memory cell M_(0,1).

[0063] As described above, the erase operation of memory block 300 issimilar to the erase operation of memory block 100. However, memoryblock 300 will exhibit greater endurance than memory block 100, becauseon average, the memory cells of memory block 300 are programmed anderased twice as often as a comparable flash memory, rather than 63 timesas often, as was the case for memory block 100. However, memory block300 is less area efficient than memory block 100, because memory block300 requires a full set of select transistors 131-138 for each row ofmemory cells.

[0064] In accordance with another embodiment of the invention, memoryblock 300 emulates an EEPROM by operating memory cells M_(0,0)-M_(0,6),ML₀ and MR₀ as 1-bit memory cells. For example, in one embodiment, onlythe right charge trapping regions of memory cells M_(0,0)-M_(0,6), ML₀and MR₀ are used to store data. In this embodiment, the left chargetrapping regions of these memory cells are not used to store data. Thus,erase operations are carried out simply by erasing the right chargetrapping region of the desired memory cell. Even though the left chargetrapping region of the right adjacent memory cell is incidentallyerased, this is irrelevant because this left charge trapping region isnot used to store data. Moreover, there is no detrimental over-erasecondition associated with the left charge trapping region under theseconditions. In this manner, memory block 300 can advantageously beoperated as EEPROM in accordance with this embodiment. In a variation ofthis embodiment, only the left charge trapping regions are used to storedata.

[0065] Although the invention has been described in connection withseveral embodiments, it is understood that this invention is not limitedto the embodiments disclosed, but is capable of various modificationswhich would be apparent to a person skilled in the art. For example,although the memory blocks have been described as having eight diffusionbit lines, four metal bit lines and eight select transistors, it isunderstood that memory blocks having different numbers of diffusion bitlines, metal bit lines and select transistors can be constructed.Moreover, although memory blocks 100 and 300 have been described ashaving 32 rows of memory cells and one row of memory cells,respectively, it is understood that other numbers of memory cell rowscan be used in other embodiments. In addition, although the chargetrapping regions have been described in connection with an ONOstructure, it is understood that these charge trapping regions can beimplemented by other layers, such as a layer of silicon oxide havingburied polysilicon islands Moreover, elements other than the describedselect transistors can be used to provide access to the memory cells.Thus, the invention is limited only by the following claims.

1. An electrically erasable programmable read only memory (EEPROM) blockcomprising: a row of 2-bit non-volatile memory cells, each of the memorycells having a first charge trapping region for storing a bit and asecond charge trapping region for storing a bit, wherein each pair ofadjacent memory cells in the row are coupled to share a common diffusionbit line; a plurality of metal bit lines; and a plurality of highvoltage select transistors coupled between the diffusion bit lines andthe metal bit lines.
 2. The EEPROM block of claim 1 , wherein the row ofmemory cells comprises a shared memory cell located at each end of therow.
 3. The EEPROM block of claim 1 , wherein there are half as manymetal bit lines as diffusion bit lines.
 4. An electrically erasableprogrammable read only memory (EEPROM) array comprising: a plurality ofrows of 2-bit non-volatile memory cells, each of the memory cells havinga first charge trapping region for storing a first bit and a secondcharge trapping region for storing a second bit; and a dedicated set ofhigh voltage select transistors coupled to each of said rows of memorycells.